Memory with multiple state cells and sensing method

Details Memory with multiple state cells and sensing method Memory with multiple state cells and sensing method

2005-01-25

2005-01-25

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S131000, C365S168000, C365S187000

Reexamination Certificate

active

06847548

ABSTRACT:
A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.

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patent: 20020037595 (2002-03-01), Hosotani
Eitan, Boaz et al.; A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell; IEEE Electron Device Letters; Nov., 2002; pp. 543-545; vol. 21; No. 11;IEEE.

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