Memory with increased write margin bitcells

Details Memory with increased write margin bitcells Memory with increased write margin bitcells

2006-11-17

2009-02-17

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000, C365S156000

Reexamination Certificate

active

07492627

ABSTRACT:
A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.

REFERENCES:
patent: 5689458 (1997-11-01), Kuriyama
patent: 6597620 (2003-07-01), McMinn
patent: 6724648 (2004-04-01), Khellah et al.
patent: 7289354 (2007-10-01), Houston
patent: 2004/0125644 (2004-07-01), Komatsuzaki
patent: 2004/0130930 (2004-07-01), Houston
patent: 2006/0056229 (2006-03-01), Maeda et al.
patent: 2007/0165448 (2007-07-01), Itoh et al.

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