Memory with function test of error detection/correction device

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371 401, G06F 1110, G06F 1100

Patent

active

049244655

ABSTRACT:
A memory device for detecting and correcting errors in stored data includes a circuit for generating an error-detection/correction code with respect to data to be stored, a memory cell array in which the data and the error-detection/correction code are stored, an error-detection/correction circuit for detecting and corrrecting errors in the data by using the error-detection/correction code when the data is read out of the memory cell array, and a function test circuit selectively and directly connected to the error-detection/correction circuit for testing the error-detection/correction circuit.

REFERENCES:
patent: 4034195 (1977-07-01), Bates
patent: 4359771 (1982-11-01), Johnson et al.
patent: 4561095 (1985-12-01), Khan
patent: 4763328 (1988-08-01), Shimoda et al.
patent: 4794597 (1988-12-01), Ooba et al.
patent: 4809273 (1989-02-01), Jackowski et al.
Barsuhn et al., Self-Testing ECC Logic, IBM Tech. Discl. Bulletin, vol. 20, No. 7, Dec. 1977, pp. 2733-2734.

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