Memory with cache register interface structure

Details Memory with cache register interface structure Memory with cache register interface structure

1988-12-27

1989-12-19

Fears, Terrell W.

Static information storage and retrieval

Addressing

Multiple port access

365 49, 365221, G11C 1300

Patent

active

048887412

ABSTRACT:
A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such that while one cache register is connected to the data input/output port, the other cache register is connected to a port of the memory. Look-ahead logic is provided to generate the next address of the memory location which is to be written into or read from with simultaneous transfer of information to or from the cache register which is connected to the memory ports.

REFERENCES:
patent: 4796232 (1989-01-01), Horse

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