Memory with address conversion table

Details Memory with address conversion table Memory with address conversion table

1999-11-04

2002-08-06

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

Reexamination Certificate

active

06430669

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory integrated circuit that forms the main memory of a computer system and, more particularly, to a memory with an address conversion table which allows high-speed access to a main memory in a virtual memory.
Generally, a computer system validates a plurality of processes simultaneously and executes them while time-divisionally distributing the hardware to the processes, thereby efficiently using the hardware resources. A virtual memory is often used to provide the same program environment to the processes. When the virtual memory is used, all processes can have an address space in the same range and independently address the memory. That is, the processes actually access different memories.
To realize such a virtual memory, address values must be converted between the memory address (virtual address) on the program and the real address (physical address) of the memory to be actually addressed.
In this case, when a table for address conversion is prepared on an external memory, a long time is required to look up the conversion table. This is because when the external memory is to be addressed, the address is converted into a physical address by looking up the external conversion table, and after this, the target external memory is addressed. To shorten the memory access time, the address conversion table is prepared in the microprocessor.
A conventional address conversion table is shown in, e.g., John L. Nennessy & David A. Patterson, “Computer Architecture a Quantitative Approach”, Second Edition 1996, Morgan Kaufmann Publisher Inc., pp. 439-447. This address conversion table will be described with reference to
FIGS. 11 and 12
.
FIG. 11
shows the arrangement of a conventional memory.
In a memory
5
which is conventionally used as a main memory, part of address data (to be referred to as an address hereinafter) input from an address bus
100
is supplied to a memory array
10
to read out data to a CAS (Column Address Select) buffer
30
. Subsequently, the remaining part of the address is supplied to the CAS buffer
30
.
In a data read, data designated by an address is extracted from the CAS buffer
30
to a data bus
101
. In a data write, a value supplied to the data bus
101
is written in a corresponding portion of the CAS buffer
30
, and the value of the CAS buffer
30
is written back to the memory array
10
. As described above, the conventional memory
5
has no function of converting the value of the address bus
100
.
FIG. 12
shows the schematic arrangement of the main memory portion of a computer in use of the memory
5
shown in FIG.
11
.
Referring to
FIG. 12
, a microprocessor
2
′ has the 64-bit data bus
101
as a memory bus. A plurality of memories
5
have 16-bit data buses
101
a
,
101
b
,
101
c
, and
101
d
, respectively. The 64-bit data bus
101
on the microprocessor
2
′ side is divided into the 16-bit data buses
101
a
,
101
b
,
10
c
, and
101
d
and connected to the memories
5
.
The address bus
100
is commonly connected to the memories. In the microprocessor
2
′, an address is output from a core
60
as a virtual address (logical address) value. The logical address output from the core
60
is divided into a logical page address
120
and page offset address
121
. The logical page address
120
is converted into a physical page address
122
by an address conversion table
61
. The physical page address
122
and page offset address
121
are combined to generate a physical address which is output to the address bus
100
. In this way, the physical address is supplied to the memories
5
, and memory cells in the memories
5
are addressed.
The address conversion table
61
in the microprocessor has only several to several ten entries because of the limitations on the number of elements and chip area of the integrated circuit constructing the microprocessor. On the other hand, a main memory
200
formed from the plurality of memories
5
has a capacity of several ten Mbytes to several Gbytes and is divided into pages each having 64 to 512 kbytes. For this reason, the main memory
200
requires a page table having several hundred to several ten thousand entries.
The address conversion table
61
in the microprocessor
2
′ can address only part of the main memory
200
. A logical address that is not present in the address conversion table
61
must be converted into a physical address by looking up the page table prepared in the main memory
200
. Hence, a long time is required to address the main memory
200
.
Even if the microprocessor
2
′ can have a large address conversion table, the main memory
200
may be expanded, resulting in a shortage of entries of the address conversion table in the microprocessor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory with an address conversion table capable of shortening the main memory access time.
In order to achieve the above object, according to the present invention, there is provided a memory comprising a memory array having a plurality of page memories addressed in accordance with a logical address on an address bus, and an address conversion table for converting the logical address assigned to the page memory into a physical address and outputting a physical page address to the page memory.


REFERENCES:
patent: 4373179 (1983-02-01), Katsumata
patent: 4933938 (1990-06-01), Sheehy
patent: 6192455 (2001-02-01), Bogin et al.
Kai Hwang, “Advanced Computer Architecture”, 1993, McGraw-Hill Inc, pp. 199-204.*
John L. Hennessy & David A. Patterson, “Computer Architecture a Quantitative Approach”, Second Edition 1996, Morgan Kaufmann Publisher Inc., pp. 439-447.

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