Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2001-11-21
2002-09-10
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S218000
Reexamination Certificate
active
06449681
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to buffer access control circuits which are used to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address, and more particularly to a buffer access control circuit which uses a simple circuit construction to carry out a process of updating the address one by one when consecutively accessing the upper buffer and the lower buffer.
There exists a type of buffer which is divided into an upper buffer and a lower buffer which are assigned the same address. When consecutively accessing the upper buffer and the lower buffer of such a buffer, an access process is carried out by updating the address one by one and accessing data regions of the buffer indicated by the successively updated address. It is desirable that this access process can be realized by use of a simple circuit construction.
2. Description of the Related Art
The access process with respect to the buffer which is divided into the upper buffer and the lower buffer which are assigned the same address, includes a first access process with respect to the buffer formed by the upper buffer and the lower buffer, and a second access process with respect to the upper buffer and the lower buffer.
In the case of the second access process, the upper buffer may be specified again as the access destination after the upper buffer is accessed or, the lower buffer may be specified again as the access destination after the lower buffer is accessed. In this case, the access to the buffer is made without updating the address. On the other hand, in the first access process, when the lower buffer is specified as the access destination after the upper buffer is accessed or, when the upper buffer is specified as the access destination after the lower buffer is accessed, the access to the buffer is made by counting up the address by one.
A description will be given of an access to a 2-byte buffer having a 1-byte upper buffer
401
and a 1-byte lower buffer
402
, by referring to
FIGS. 1 through 4
.
FIG. 1
shows a case where a write request is first issued to write a data A by specifying the lower buffer
402
as an access destination. In this case, the data A is written in the lower buffer
402
at a location {circle around (1)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by again specifying the lower buffer
402
as the access destination, the data B is written in the lower buffer
402
at the location {circle around (1)} according to the algorithm described above, thereby rewriting the previously written data A with the data B.
Similarly,
FIG. 2
shows a case where a write request is first issued to write a data A by specifying the upper buffer
401
as an access destination. In this case, the data A is written in the upper buffer
401
at a location {circle around (2)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by again specifying the upper buffer
401
as the access destination, the data B is written in the upper buffer
401
at the location {circle around (2)} according to the algorithm described above, thereby rewriting the previously written data A with the data B.
On the other hand,
FIG. 3
shows a case where a write request is first issued to write a data A by specifying the lower buffer
402
as an access destination. In this case, the data A is written in the lower buffer
402
at a location {circle around (1)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by specifying the upper buffer
401
as the access destination, the data B is written in the upper buffer
401
at the location {circle around (2)} according to the algorithm described above. Thereafter, the present address is counted up by one.
Next, when a write request is issued to write a data C by specifying the lower buffer
402
as the access destination, the data C is written in the lower buffer
402
at a location {circle around (3)} specified by the updated present address, according to the algorithm described above. In addition, when a write request is then issued to write the data C by specifying the upper buffer
401
as the access destination, the data C is written in the upper buffer
401
at the location {circle around (4)} specified by the updated present address, according to the algorithm described above.
Similarly,
FIG. 4
shows a case where a write request is first issued to write a data A by specifying the upper buffer
401
as an access destination. In this case, the data A is written in the upper buffer
401
at the location {circle around (2)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by specifying the lower buffer
402
as the access destination, the data B is written in the lower buffer
401
at the location {circle around (1)} according to the algorithm described above. Thereafter, the present address is counted up by one.
Next, when a write request is issued to write a data C by specifying the upper buffer
401
as the access destination, the data C is written in the upper buffer
401
at the location {circle around (4)} specified by the updated present address, according to the algorithm described above. In addition, when a write request is then issued to write the data C by specifying the lower buffer
402
as the access destination, the data C is written in the lower buffer
402
at the location {circle around (3)} specified by the updated present address, according to the algorithm described above.
FIG. 5
is a system block diagram showing an example of a conventional buffer access control circuit which carries out the access process of the buffer
400
described above.
The buffer access control circuit shown in
FIG. 5
includes D-type flip-flop circuits
100
,
101
and
105
, an AND circuit
102
, a check signal generating circuit
103
, an address counter (ADR. CTR.) circuit
104
, and a delay circuit
106
which are connected as shown, with respect to the buffer
400
. The flipflop
100
latches a power supply voltage Vcc at a falling edge of a lower buffer access signal LBA which has a low level when there is an instruction to access the lower buffer
402
. The flip-flop circuit
101
latches the power supply voltage Vcc at a falling edge of an upper buffer access signal UBA which has a low level when there is an instruction to access the upper buffer
401
. The AND circuit
102
obtains a logical product AND of data det-L and det-H latched by the flip-flop circuits
100
and
101
. The check signal generating circuit
103
generates a check signal chk which has a low level when one of the lower buffer access signal LBA and the upper buffer access signal UBA has a low level. The address counter circuit
104
inputs an output signal andO of the AND circuit
102
at a rising edge of the check signal chk which is applied to the clock (CK) input of the address counter circuit
104
, and counts up a counted value, which becomes the buffer address, when the output signal andO of the AND circuit
102
has a high level. The flip-flop (FF) circuit
105
latches the output signal andO of the AND circuit
102
at the rising edge of the check signal chk, and outputs an inverted output signal. The delay circuit
106
delays the inverted output signal of the flip-flop circuit
105
, and supplies a clear signal CL to clear terminals of the flip-flop circuits
100
,
101
and
105
. Each of the flip-flop circuits
100
,
101
and
105
carries out a clear process at a rising edge of the clear signal CL input to the clear terminal thereof.
According to the buffer access control circuit having the construction shown in
FIG. 5
, when the lower buffer
402
is specified as the access destination and the upper buffer
401
is next specified as the access destination, the A
Gama Shinkichi
Hayashi Tomohiro
Nagase Takeshi
Okumura Yoshiki
Takamatsuya Yoshihiro
Fujitsu Limited
Gossage Glenn
Staas & Halsey , LLP
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