Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-11-22
2005-11-22
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C714S042000
Reexamination Certificate
active
06967879
ABSTRACT:
When a redundancy circuit is provided to relieve the inferiority of a semiconductor storage device, and then, the semiconductor storage device has no defect, power is inconveniently supplied even to the unused redundancy circuit to generate unnecessary leakage current.A self-diagnosis circuit for a semiconductor storage device is provided to perform the self-diagnosis of the semiconductor storage device upon turning on a power source. Power (2) is supplied to a redundancy circuit part and power (1) is supplied to a circuit part except the redundancy circuit part. When the semiconductor storage device has no defect as a result of the self-diagnosis, a control for turning off the power (2) of the redundancy circuit part is performed.
REFERENCES:
patent: 5862088 (1999-01-01), Takemoto et al.
patent: 5946250 (1999-08-01), Suzuki
patent: 6438044 (2002-08-01), Fukuda
patent: 6556479 (2003-04-01), Makuta et al.
patent: 6668348 (2003-12-01), Nakamura
patent: 6711705 (2004-03-01), Yasui
patent: 6762963 (2004-07-01), Inoue et al.
patent: 11-238393 (1999-08-01), None
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Phan Trong
LandOfFree
Memory trouble relief circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory trouble relief circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory trouble relief circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3453344