Memory transistor having underlapped floating gate

Details Memory transistor having underlapped floating gate Memory transistor having underlapped floating gate

1995-06-06

1999-04-13

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, H01L 29788

Patent

active

058941479

ABSTRACT:
An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor; and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.

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