Memory transistor array utilizing insulated word lines as...

Details Memory transistor array utilizing insulated word lines as... Memory transistor array utilizing insulated word lines as...

2006-04-04

2006-04-04

Chambliss, Alonzo (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S692000, C257S696000, C257S700000, C257S758000, C257S773000

Reexamination Certificate

active

07023061

ABSTRACT:
A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

REFERENCES:
patent: 5306941 (1994-04-01), Yoshida
patent: 5877537 (1999-03-01), Aoki
patent: 6381166 (2002-04-01), Yoshida et al.
patent: 6765271 (2004-07-01), Iijima
patent: 6891262 (2005-05-01), Nomoto et al.
patent: 2001/0052958 (2001-12-01), Ogawa

Affiliated with

Also associated with

Rating

Memory transistor array utilizing insulated word lines as... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory transistor array utilizing insulated word lines as..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory transistor array utilizing insulated word lines as... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3615025