Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
1999-09-30
2002-10-15
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
C711S005000, C710S002000, C710S300000, C710S305000
Reexamination Certificate
active
06467013
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to data communications in a computer system, and more specifically, to a transceiver that enables a single main memory channel to communicate with multiple expansion memory channels.
2. Background Information
Computer systems rely heavily upon Dynamic Random Access Memories (“DRAMs”) to implement system memories due to their simplicity, affordability and memory density. However, it is increasingly difficult to design memory systems that satisfy the size and performance requirements for modern computer systems using DRAMs connected by conventional bus architectures. To overcome these limitations, a memory subsystem can be constructed using a memory channel architecture. Intelligent memory devices are connected by a narrow, high-speed bus, termed a channel. Packets of information are used to communicate between the memory controller and the memory devices. Direct Rambus™ architecture using Rambus® channels is an example of a memory subsystem using a memory channel architecture.
A Rambuse® channel includes a number of high-speed, controlled impedance, matched transmission lines. The length of the Rambuse® channel is limited by the electrical requirements and, as a result, the number of memory devices that can be supported by one channel is limited. The Direct Rambus™ architecture provides for a maximum of 32 Rambus DRAM (RDRAM®) devices on a Rambuse® channel with a maximum of 128 megabytes (MB) per RDRAM® and 4 gigabytes (GB) on the channel. Presently, the largest RDRAM device available is a 32 MB device reducing the capacity of a Rambus® channel to 1 GB. Some computer systems, such as systems that support large in-memory databases, have a need for very large memory subsystems made possible by 64 bit computer architectures. A computer system can be constructed with multiple Rambus® Memory Controllers (MCHs) to support more than 32 RDRAM® devices. However, the use of multiple MCHs increases system cost and complexity because of the additional logic required for the MCHs and the necessary interconnecting logic to provide a seamless memory across multiple controllers.
U.S. Pat. No. 5,319,755, assigned to Rambus Inc., discloses a multiple bus (channel) structure using transceivers that can be used when the data rate of a single bus (channel) is adequate but more memory devices are required than can be supported by a single-bus (channel). The transceivers described either repeat all signals from the memory controller to the multiple channels or, at least repeat some signals on the multiple channels that are extraneous. In a multiple memory channel structure, the repeating of extraneous signals, signals not directed to a device on a particular expansion memory channel, degrades the bandwidth of the memory subsystem. Further, there are a number of channel service request packets that must be sent by the controller to maintain the memory array. As the number of memory devices increases, the amount of bandwidth consumed by these channel service requests becomes significant. Accordingly, there is a need for a more sophisticated transceiver that recognizes signals addressed to devices on its expansion memory channel, repeating only those signals required by devices on its expansion memory channel, and that provides a mechanism to reduce the bandwidth consumed by the overhead of channel service request for the large number of devices found in a multiple memory channel configuration.
SUMMARY
A memory repeater hub comprising a main memory channel interface circuit, an expansion control channel interface circuit, and an expansion memory channel interface circuit. The main memory channel interface circuit receives a memory control packet and a memory data packet from a main memory channel. The expansion control channel interface circuit receives a first expansion control packet and a second expansion control packet from an expansion control channel. The expansion memory channel interface circuit selectively transmits the memory control packet to an expansion memory channel responsive to the first expansion control packet, and selectively transmits the memory data packet to the expansion memory channel responsive to the second expansion control packet.
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patent: 6076139 (2000-06-01), Welker
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patent: WO-9934294 (1998-12-01), None
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
McLean Kimberly
Yoo Do Hyun
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