Memory testing through cumulative word line activation

Details Memory testing through cumulative word line activation Memory testing through cumulative word line activation

1995-03-06

1996-02-27

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365194, 36523006, G11C 700

Patent

active

054954487

ABSTRACT:
An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises I.sub.DDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for I.sub.DDQ test purposes only.

REFERENCES:
patent: 4779272 (1988-10-01), Kohda et al.
patent: 5258954 (1993-11-01), Furuyama
patent: 5293340 (1994-03-01), Fujita
patent: 5371712 (1994-12-01), Oguchi et al.
"A New Testing Acceleration Chip for Low-Cost Memory Tests", M. Inoue et al, IEEE Design & Test of Computers, Mar. 1993, pp. 15-19.

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