Memory testing method and apparatus

Details Memory testing method and apparatus Memory testing method and apparatus

2005-05-31

2005-05-31

Chase, Shelly A (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06901541

ABSTRACT:
A method of testing memory devices includes issuing a command to a Flash memory device, simultaneously monitoring at least one data bit of each Flash memory device for a ready indication, and then verifying the command was performed successfully in each Flash memory device. The command can be an erase command, a write command, or the like. The simultaneous monitoring can be performed by simultaneously asserting signals on output enable nodes of the memory devices, and monitoring bidirectional tester channels dedicated for this purpose. A test fixture includes memory device receptacles, a tester interface, and conductive paths to couple the tester interface to the memory device receptacles. The conductive paths include paths for dedicated bidirectional tester channels and shared bidirectional tester channels.

REFERENCES:
patent: 5561628 (1996-10-01), Terada et al.
patent: 5604756 (1997-02-01), Kawata
patent: 5787096 (1998-07-01), Roberts et al.
patent: 5936901 (1999-08-01), Wong et al.
patent: 5999446 (1999-12-01), Harari et al.
patent: 6081467 (2000-06-01), Waller
patent: 6219289 (2001-04-01), Satoh et al.
patent: 6349396 (2002-02-01), Akram

Affiliated with

Also associated with

Rating

Memory testing method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory testing method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory testing method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3390100