Memory testing device and method

Details Memory testing device and method Memory testing device and method

2007-07-10

2007-07-10

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S736000, C365S201000

Reexamination Certificate

active

10172454

ABSTRACT:
A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.

REFERENCES:
patent: 5587950 (1996-12-01), Sawada et al.
patent: 6173238 (2001-01-01), Fujisaki
patent: 6243422 (2001-06-01), Urabe et al.
patent: 6361501 (2002-03-01), Amano et al.
patent: 6543015 (2003-04-01), Wang et al.
patent: 6877118 (2005-04-01), Oshima et al.

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