Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-07-07
2003-02-18
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000, C365S201000
Reexamination Certificate
active
06523143
ABSTRACT:
This patent application claims priority based on a Japanese patent application, H11-192627 filed on Jul. 7, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing apparatus for testing memory devices, and it particularly relates to the memory testing device capable of performing failure analysis on the memory devices.
2. Description of the Related Art
In recent years, high integration of the memory devices has been significant due to developments in semiconductor manufacturing processes. Thus, there are many occasions where large-scale newly developed memory needs to be tested. Evaluating a whole memory devices as a failure as a result of a single failure cell (defective spot) in the memory device is not ideal in terms of productivity or yield.
Thus, there is available a method in which the memory device is equipped with a redundant structure in advance, so that a failure cell can be saved by replacing the failure cell with a spare memory. In this method, a memory device which is non-defective as a whole can be produced even though part of cell is defective, so that the yield can be improved. Moreover, a defective spot can be scrutinized so as to perform the failure analysis for finding and mending a cause of the failure, thus being desirable in the course of improving the yield of the devices.
FIG. 1
shows how a pattern generator
10
is connected to a failure memory
20
in the conventional memory testing apparatus, which tests a memory under test. The pattern generator
10
includes a sequence control unit
12
; an address generator
14
; a data generator
16
; and a control signal generator
18
. The address generator
14
includes: an internal address generator
26
; an address converting unit
28
; and selectors
30
a
and
30
b
. Moreover, the failure analysis memory
20
includes: a defective data storing memory
22
; and a failure history storing memory
24
. The defective data storing memory has the same capacity as that of the memory device under test.
The sequence control unit
12
generates a sequence signal
32
that controls the sequence of the address generator
14
, data generator
16
and control signal generator
18
. In the address generator
14
, the internal address generator
26
generates an internal address corresponding to the cell configuration of the memory under test, based on the sequence control signal
32
. Here, the memory cell of the memory device is configured in the optimum position, so that an address to be input to the address pin of the memory device is not necessarily matched up with the internal address within the cell. This is because the wiring, which connects the address pin to each cell, is formed by a request concerning the physical configuration and arrangement. Thus, the address converting unit
28
converts the internal address to an input address which specifies the cell of the memory under test that the internal address primarily addresses, from the address pin of the memory under test. The internal address corresponds to the input address in a one-to-one manner. The selector
30
a
selects the input address and outputs the input address signal
34
to the memory under test. The input address signal
34
that is input to the memory under test accesses a memory cell specified by the corresponding internal address.
When a defective spot is found in the memory under test as a result of the test, the pattern generator
10
supplies to the failure analysis memory
20
the data on defective saving and/or failure analysis. The selector
30
b
supplies an address signal
36
which corresponds to the address of the defective spot of the memory under test, to the address pin of the defective data storing memory
22
and the data pin of the failure history storing memory
24
. The address signal
37
is either the internal address signal corresponding to the internal cell of the memory under test, or the input address in which the internal address signal is converted based on the physical configuration and arrangement of the internal cell of the memory under test and the address pins. Moreover, the data generator
16
supplies to the data pin of the failure history storing memory
24
, a data signal
38
acquired at the time the detective spot was detected. At the same time, the control signal generator
18
supplies to the data pin of the failure history storing memory
24
, a control signal
40
acquired at the time of detection of the defective spot. The defective data is supplied to the data pin of the failure data storing memory
22
while an increment signal is supplied to the address pin of the failure history storing memory
24
.
As a result thereof, in the defective data storing memory
22
, the defective data is written to an address corresponding to an address cell of the defective cell of the memory under test. Moreover, in the failure history storing memory
24
, the failure history data such as data and address at the time of testing are written thereto in the order that the failures were detected. Data stored in the defective data storing memory
22
and the failure history storing memory
24
will be utilized in saving the defective cells as well as in failure analysis at a later stage.
Since in the conventional memory testing apparatus there exists only a single signal transmission line system between the pattern generator
10
and each of the defective data storing memory
22
and the failure history storing memory
24
, the pattern generator
10
can only supply either the internal address or the input address signal to the defective data storing memory
22
and the failure history storing memory
24
.
Thus, in the event that there is a request for supplying the internal address to the defective data storing memory
22
and for supplying the input address signal to the failure history storing memory
24
, two steps of operations must be taken in the conventional memory testing apparatus. Namely, in satisfying this request, first the internal address signal indicating the defective address is stored in the defective data storing memory
22
, and it is further required that, next, a program for the test is changed, so that the input address corresponding to the defective address is supplied to the failure history storing memory
24
.
In that case, the test must be carried out at least twice, in order to store the data for use in the failure analysis, to the failure analysis memory
20
. There is a problem in that development cost increases and hence a device will cost more, if it takes a longer time to perform the failure analysis. In this manner, it remains an important subject matter in the conventional practice, that data transmission time from the pattern generator
10
to the failure analysis memory
20
shall be shortened as much as possible.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a memory testing apparatus which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to an aspect of the present invention, a memory testing apparatus for testing a memory, comprises: a pattern generator which outputs: an input address signal supplied to an address pin of the memory, an input test signal, including an input data signal, supplied to a data pin of the memory, and an expectation value data signal which is an expectation value data signal that is to be output, based on the input test signal, from the memory, as a response result from a normal memory device; a signal input-output unit which supplies the input test signal to the memory and receives an output data signal from the memory; a comparator which compares the output data signal with the expectation value data and outputs a defect-indicating data indicative of existence of a defective spot in the memory; a defective data stori
Advantest Corporation
Rosenthal & Osha L.L.P.
Tu Christine T.
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