Memory testing apparatus

Details Memory testing apparatus Memory testing apparatus

1999-08-13

2002-07-23

Beausoleil, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S723000, C365S201000

Reexamination Certificate

active

06425095

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various kinds of semiconductor memories including a memory being constructed by, for example, a semiconductor integrated circuit (hereinafter, referred to as IC), and more particularly, to an improvement in a memory testing apparatus provided with a failure relief analyzer for counting the number of failure memory cells of a tested semiconductor memory to determine whether the relief of the tested semiconductor memory can be carried out or not. (Hereinafter, a memory being constructed by a semiconductor integrated circuit is referred to as IC memory.)
2. Description of the Related Art
Recently, storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a reduction of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being reduced, there are manufactured IC memories in each of which, for example, one or more failure memory cells can be electrically replaced by a substitute or alternative memory cell (also called a spare line, relief line or redundancy circuit). As will be described later, the IC memory of this kind is called a memory of redundancy structure in this technical field, and a decision as to whether the redundancy-structured memory can be relieved or not is rendered by a failure relief analyzer.
FIG. 2
shows a block diagram of a general construction of an example of the prior memory testing apparatus having a conventional failure relief analyzer. As is well known, this memory testing apparatus comprises a timing generator
10
, a pattern generator
20
, a waveform shaping device
30
, a logical comparator
40
, a failure analysis memory
50
and a failure relief analyzer
6
. Further, in the following description, a case that the memory testing apparatus will test IC memories will be described. In case of testing various kinds of semiconductor memories other than IC memories by the memory testing apparatus, however, they will be tested in similar manner.
The timing generator
10
generates a clock CLK constituting a reference for the entire memory testing apparatus and various timing signals (not shown). Based on (in synchronism with) the reference clock CLK supplied from the timing generator
10
, the pattern generator
20
generates address data ADRD, test pattern data PTND and control data CNTLD all of which are to be supplied to an IC memory under test (hereinafter, simply refereed to as memory under test) MUT. These data signals are inputted to the waveform shaping device
30
where they are converted, on the basis of timing signals (not shown) supplied from the timing generator
10
, into an address signal ADR, a test pattern signal PTN and a control signal CNTL, respectively, having real waveforms required for testing the memory under test MUT. Thereafter, these signals are applied to the memory under test MUT.
The read/write operations of the memory under test MUT are controlled by the control signal CNTL supplied thereto through the waveform shaping device
30
so that a writing of the test pattern signal PTN applied from the waveform shaping device
30
in the memory under test and a reading of the written test pattern signal can be performed. The test pattern signal PTN written in the memory under test MUT is read out therefrom later, and the read-out response signal RPD is supplied to the logical comparator
40
where the response signal RPD is logically compared with an expected value pattern data (signal) EXP supplied from the pattern generator
20
to detect whether or not there is an anticoincidence between the two signals.
If the two signals do not coincide with each other, the logical comparator
40
determines that the memory cell having an address of the memory under test MUT from which the response signal RPD has been read out is defective (failure), and generates a failure signal FAIL indicating that fact. When the failure signal FAIL is generated from the logical comparator
40
, usually, a logical “1” signal (data) is stored in a memory cell of the failure analysis memory
50
specified by address data ADRD (in practice, an address signal ADR obtained by converting this address data into a physical address) from the pattern generator
20
. In general, this logical “1” signal is stored in the same address of the failure analysis memory
50
as that of the failure memory cell of the memory under test MUT.
On the contrary, if the response signal RPD coincides with the expected value pattern data EXP, the logical comparator
40
determines that the memory cell having an address of the memory under test MUT from which the response signal RPD has been read out is not defective (pass), and generates a pass signal indicating that fact. This pass signal is not stored in the failure analysis memory
50
.
In such a way, the information on the failure memory cells (logical “1s”) of the memory under test MUT generated during a series of tests is stored in the failure analysis memory
50
. After the testing has been completed, the failure data stored in the failure analysis memory
50
are read out therefrom into the failure relief analyzer
6
, thereby to carry out a failure analysis for the memory under test MUT.
The failure analysis memory
50
has its operating rate or speed and its memory capacity equivalent to those of the memory under test MUT, and the same address signal as the address signal ADR applied to the memory under test is also applied to this failure analysis memory
50
. In addition, the failure analysis memory
50
is initialized prior to the start of a testing. For example, when initialized, the failure analysis memory
50
has data of logical “0s” written in all of the addresses thereof. Every time a failure signal FAIL indicating the anti-coincidence is generated from the logical comparator
40
during a testing of a memory under test MUT, a failure data of logical “1” indicating the failure of a memory cell is written in the same address of the failure analysis memory
50
as that of the memory cell of the memory under test MUT from which that anti-coincidence has been generated.
The failure relief analyzer
6
separately and simultaneously counts the total number of failure memory cells stored in the failure analysis memory
50
, and the number of failure memory cells on each address line of row (lateral) address lines and column (longitudinal) address lines stored in the failure analysis memory
50
, and analyzes to determine whether the relief of the tested memory can be done or not by use of relief lines, i.e., spare memory cells (spare lines or redundancy circuits) provided in the memory under test MUT. A memory having such relief lines provided therein is, as mentioned above, called a redundancy-structured memory in this technical field.
Here, a brief explanation will be given regarding a redundancy-structured memory.
FIG. 3
shows in outline an arrangement of an example of such redundancy-structured memories. A memory under test MUT is provided with, in addition to a memory cell array (main storage portion) MCA where memory cells are arrayed in rows and in columns, row address relief lines SR and column address relief lines SC formed on the periphery of the memory cell array MCA. The memory cell array MCA, the row address relief lines SR and the column address relief lines SC are formed in the same semiconductor chip. In this example, a case is shown where two row address relief lines SR are disposed along one side of the row address direction of the memory cell array MCA and two column address relief lines SC are disposed along one side of the column address direction of the memory cell array MCA, respectively. However, it is needless to say that the number of relief lines and the positions where these relief lines are disposed are not limited to the example as illustrated.
As a result

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