Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-06-12
2000-04-04
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714738, G11C 2900
Patent
active
060473932
ABSTRACT:
There is provided a memory testing apparatus which can complete a DC test FOR a memory in a short time period. A pattern generator 2 comprises a hold time setting device 2A for setting a hold time during which a test signal of a predetermined pattern is kept being applied to a memory under test 4, a hold mode control device 2B, activated upon setting of a hold time, for controlling the pattern generator 2 in a hold mode, a DC test start command generating device 2C for generating a DC test start command DCS for starting a DC test of the memory, a pattern end detecting device 2D for detecting when the DC test for the memory is completed, and an end signal generating device 2E for generating a pattern end signal PGEND indicating the completion of the DC test, and there is provided a signal line 5 for transmitting the DC test start command DCS to a DC test unit 3, and further, the DC test unit 3 comprises a decision device 3A for comparing a voltage or a current taken out from the memory with a reference value and a failure analysis memory 3B for storing therein a failure address of the memory.
REFERENCES:
patent: 4775977 (1988-10-01), Hehara
patent: 5528136 (1996-06-01), Rogoff et al.
patent: 5889936 (1999-03-01), Chan
patent: 5909448 (1999-06-01), Takahashi
patent: 5917833 (1999-06-01), Sato
patent: 5978949 (1999-11-01), Terayama
Advantest Corporation
Lathrop David N.
Nguyen Hoa T.
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