Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-07-31
2007-07-31
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
10727239
ABSTRACT:
A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.
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Doney et al., RAM Read/Write Controller During Self-Test, Research Disclosure, Aug. 1989, No. 304, copyright—Kenneth Mason Publications Ltd, England, 1 page.
Ouellette Michael R.
Rowland Jeremy P.
Britt Cynthia
International Business Machines - Corporation
Schmeiser Olsen & Watts
Steinberg William H.
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