Memory test system having a pattern generator for a multi-bit te

Details Memory test system having a pattern generator for a multi-bit te Memory test system having a pattern generator for a multi-bit te

1996-08-26

1997-08-19

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

056595492

ABSTRACT:
A semiconductor memory testing methods and apparatus are arranged to accommodate a multi-bit mode of testing operation in which the memory under test itself includes internal peripheral circuits for comparing the contents of memory cells for multi-bit testing, and outputting a single-bit indicative of whether or not said multiple cells have the same state. The present invention includes methods and apparatus for determining the polarity of a memory cell under test, and taking that polarity into account informing expected data to be compared to the output of the memory under test.

REFERENCES:
patent: 4835774 (1989-05-01), Ooshima et al.

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