Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-08-13
2000-05-09
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714743, G01R 3128, G11C 2900
Patent
active
060618132
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a memory testing apparatus which can test either of parallel input/parallel output type memories and serial input/serial output type memories and can separately store therein positions of failure memory cells of a memory resulted from a memory test, thereby to perform a failure analysis of the tested memory.
BACKGROUND ART
An ordinary memory is constructed such that it has input terminals the number of which corresponds to the number of bits of a data to be written therein, output terminals the number of which corresponds to the number of bits of a data to be read out therefrom, and address terminals the number of which corresponds to the number of bits of an address signal, wherein parallel data and a parallel address signal are supplied to the plurality of input terminals and the plurality of address terminals respectively to store the parallel data in the memory and a parallel address signal is supplied to the address terminals to read the stored data from the plurality of the output terminals as parallel data. That is, the ordinary memory is a parallel input/parallel output type memory. Further, the address terminals are generally used in common for write and read operations of parallel data.
In a memory testing apparatus, parallel data read out of a memory under test are logically compared with parallel expected value data in logical comparator means. Parallel failure data resulted from the logical comparisons are supplied to a failure analysis memory and positions of failure memory cells of the tested memory are stored in memory cells of the failure analysis memory at cell positions thereof having their addresses corresponding to those of the cell positions of the tested memory. The information of the positions of failure memory cells and the number of failure memory cells stored in the failure analysis memory are utilized in performing a failure analysis of the tested memory and the like.
In recent years, there has been developed a memory having the least terminals possible. The memory of this type has therein a shift register train (a series of shift registers) called "SCAN chain" in this technical field. Such memory is arranged that an input terminal of the first stage shift register and an output terminal of the last stage shift register of the shift register train are led out therefrom to the outside, that an address signal and data to be written are inputted from this input terminal to the shift register train as a serial signal and are sequentially fed into input side shift registers of the shift register train, that the input data serially supplied to the shift register train are taken out from the input side shift registers in parallel and are stored in the memory for each address, that the data stored in the memory are read out in parallel thereof and are taken in output side shift registers of the shift register train as a parallel signal, and that the parallel data stored in output side shift registers are taken out from the output terminal of the last stage shift register of the shift register train as a serial signal by sequentially shifting the shift register train.
In such a way, by constructing a memory as a serial input/serial output type memory structure, there is obtained an advantage that the number of terminals of the memory can be reduced to a minimum.
FIG. 4 illustrates the internal structure of an example of the serial input/serial output type memory. In the drawing the serial input/serial output type memory which is to be a memory under test is denoted as a whole by a reference numeral 12. This memory under test 12 includes a built-in memory cell array 12A and a shift register train called SCAN chain. There are provided, in this example, four input terminals T0-T3 and four output terminals T4-T7 in the memory cell array 12A. Therefore, the shift register train is correspondingly constructed such that four shift registers R0-R3 disposed in the input side thereof and four shift registers R4-R7 disposed in the output side the
REFERENCES:
patent: 5481671 (1996-01-01), Fujisaki
patent: 5530805 (1996-06-01), Tanabe
patent: 5831989 (1998-11-01), Fujisaki
patent: 5841785 (1998-11-01), Suzuki
patent: 5994913 (1999-11-01), Lee
Advantest Corporation
Lathrop David N.
Nguyen Hoa T.
LandOfFree
Memory test set does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory test set, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory test set will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1075734