Memory test mode for charge retention testing

Details Memory test mode for charge retention testing Memory test mode for charge retention testing

2007-06-28

2009-06-09

Le, Vu A (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S201000

Reexamination Certificate

active

07545698

ABSTRACT:
One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer circuit external to the memory circuit die. Other embodiments are described and claimed.

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