Memory test mode circuit

Details Memory test mode circuit Memory test mode circuit

1998-04-21

2000-12-26

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

305201, G11C 2900

Patent

active

061675431

ABSTRACT:
A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used with some of the other input pins. Each of the non-standard signal levels are detected by a separate signal level detection circuit. A predetermined combination of input signals then provides a control signal which sets the integrated-circuit into a predetermined test mode. A non-standard Vcc/2 signal level is detected by determining that it is above a predetermined low threshold level of 1/4 Vcc and below a predetermined high threshold level of 3/4 Vcc. Additional non-standard input signal levels which are close to Vcc and Vss are also used. A chip enable (CEX) signal is used to enable the signal level detection circuit when a chip is enabled. A delay circuit is serially coupled to the output terminal of the signal level detection circuit to require the input signals to have a predetermined minimum time duration.

REFERENCES:
patent: 5727001 (1998-03-01), Loughmiller
patent: 5847595 (1998-12-01), Kano et al.

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