Memory test device with write and pseudo write signals

Details Memory test device with write and pseudo write signals Memory test device with write and pseudo write signals

1979-11-27

1981-05-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

365190, 365200, G11C 2900

Patent

active

042675839

ABSTRACT:
A memory device having a test function for detecting abnormal memory cells having low hold ability is disclosed. The memory device characteristically comprises a first write control circuit which operates in a normal write mode and a second write control circuit which operates in a pseudo write mode to supply a pseudo write signal lower than a threshold value at which the state or content of the normal memory cell is changed or inverted, to the memory cell to be tested. In such a pseudo write mode, the state of the normal memory cell remains unchanged, but if the tested memory cell is abnormal, its state is changed. After the pseudo write mode, the tested memory cell can be detected to be normal or abnormal by reading out the content of the tested memory cell.

REFERENCES:
Heuber et al., "Storage Cell Disturb Test", IBM Tech. Disc. Bul., vol. 20, No. 8, 1/78, pp. 3175-3176.

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