Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-07-28
2001-11-13
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S738000, C365S200000, C365S201000
Reexamination Certificate
active
06317851
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory test circuit and a semiconductor integrated circuit into which the memory test circuit is incorporated, and more particularly to a memory test circuit suitable for being built in a hybrid integrated circuit of a microprocessing unit (MPU) and a memory and the hybrid IC of MPU and the memory including the memory test circuit.
2. Description of the Related Art
As semiconductor technology makes progress, the performance of a semiconductor integrated circuit is enhanced year by year and the operational frequency of a microprocessing unit (MPU) currently reaches several hundreds MHz. However, the operational frequency of a bus between MPU and a memory LSI is as low as scores MHz because of restriction such as the delay time of wiring on a printed board. Therefore, when an MPU chip and a memory LSI chip are connected via wiring on a printed board, the performance of MPU cannot be sufficiently utilized. To enhance data transfer rate via wiring on a printed board, a trial of widening bus width (increasing the number of buses) is also made, however, there is a limit because of difficulty in designing a printed board and the restriction of the number of pins in a package. Therefore, recently, hybrid LSI of MPU and a memory in which MPU and the memory are integrated on the same semiconductor substrate attracts attention according to pages 46-53 in the March number of Nikkei Micro Device published in 1996.
As MPU and a memory are not connected via wiring on a printed board but directly connected via the internal bus of a semiconductor chip in such hybrid LSI of MPU and the memory, the length of the bus is reduced and therefore, the operational frequency of the bus can be speed up. Bus width can be also readily widened. Therefore, the velocity performance of a system can be enhanced. Approximately scores-Mbit dynamic RAM (DRAM) is mounted on hybrid LSI of MPU and a memory which is recently disclosed. It is conceivable that as semiconductor miniaturizing technology makes progress, the capacity of a mounted memory will be greatly increased the in future.
When the capacity of a mounted memory is increased, time required for testing the memory is extended. In addition, in hybrid LSI of MPU and a memory, as generally, an internal memory cannot be directly accessed from an external device and is accessed via MPU under the control of MPU, a memory test circuit for directly outputting data on an internal bus connecting the memory and MPU to an external device without via MPU and for directly supplying data from an external device to the internal bus without via MPU is required to test the memory separately from MPU.
Therefore, it is conceivable that a device to make a memory test in such LSI in short time will be more important in the future.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a memory test circuit in which time required for a memory test is reduced.
Another object of the present invention is to provide a memory test circuit in which time required for a memory test is reduced and which can locate a failure in short time if the failure is discovered in a memory test.
Further another object of the present invention is to provide a memory test circuit suitable for mounting the same on a hybrid LSI of MPU and a memory.
Furthermore another object of the present invention is to provide hybrid LSI of MPU and a memory on which a memory test circuit in which time for a test is short is mounted.
The other object of the present invention is to provide a memory test circuit which does not require multiple terminals for a test.
A memory test circuit according to the present invention is provided with first means for writing data at one logical level to any memory cell in a semiconductor memory, second means for reading data from the above any memory cell to which the data at one logical level is written, third means for detecting whether data at the other logical level different from the above one logical level is included or not in data read by the above second means, fourth means for writing data at the above other logical level to the above any memory cell, fifth means for reading data from any memory cell to which data at the above other logical level is written, and sixth means for detecting whether data at the above one logical level is included or not in data read by the fifth means.
The memory test circuit according to the present invention is provided with stripe data generating means for generating stripe data based upon a block address signal and composed of plural bits, means for writing the above stripe data to a predetermined address of a memory, means for reading information written to the above predetermined address of the memory, and a comparison means for judging whether the above read information is equivalent to the above stripe data or not, and characterized in that the above stripe data generating means generates stripe data in which one logical level and the other logical level are alternately repeated in response to a first state of the above block address signal and generates stripe data in which one logical level which continues at least twice and the other logical level which continues at least twice are alternately repeated in response to a second state of the block address signal.
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patent: 5541942 (1996-07-01), Strouss
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“DRAM”, Nikkei Microdevices, 1996, pp. 46-53 Mar. 1996 (in Japanese).
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Tu Christine T.
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