Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-08-31
2002-12-31
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000, C365S201000
Reexamination Certificate
active
06502214
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory test circuit for testing a semiconductor memory device, and more particularly to a memory test circuit capable of reducing memory test time.
2. Background of the Related Art
Generally, a memory unit includes a 256K standard cell array, a wordline driving circuit for driving wordlines, and eight mats, each of which includes a sense amplifier. Eight memory units constitutes a 16M DRAM. The number of main amps used in a 16M DRAM ranges between 16 and 64. By way of example, a 16M DRAM that uses 32 main amps will be discussed.
FIG. 1
is a block diagram of a related art memory test circuit. As shown therein, the memory test circuit includes first to eighth mats MAT
1
-MAT
8
, each consisting of a 256K standard cell array, a wordline driving circuit for driving wordlines, and a sense amp. Local input/output lines
1
and global input/output lines
2
transfer information to the first to eighth mats MAT
1
-MAT
8
, or transfer out information stored in the mats MAT
1
-MAT
8
. First to ninth mat switches MSW
1
-MSW
9
selectively connect or disconnect the local input/output lines
1
with the global input/output lines
2
, and first to fourth main amps MA
1
-MA
4
amplify data in the global input/output lines
2
. Finally, a comparing unit COMP compares outputs from the first to fourth main amps MA
1
-MA
4
.
In a normal operation, that is when simply performing a reading operation, data written in a memory cell of a memory cell array of a selected mat are outputted to the corresponding local input/output line
1
through a corresponding bit line. Then, the data in the local input/output line
1
are outputted to the global input/output line
2
through the corresponding mat switch MSW
1
-MSW
9
. The main amp MA
1
-MA
4
amplifies the inputted data and outputs it to an output buffer (not shown).
In a test mode operation, the test time is reduced by decreasing the number of addresses that are generated. Thus, all of the first to fourth main amps MA
1
-MA
4
are operated and outputs from the first to fourth main amps are compressed by using a logic device that operates the 16M DRAM as 1M DRAM. In other words, in the test mode operation, the data loaded in the global input/output line
2
are not distinguished by the addresses, as in the normal operation, and are inputted to the main amps MA
1
-MA
4
and all amplified. Accordingly, the data amplified by the main amps MA
1
-MA
4
are connected to the comparing unit COMP, which supplies a single data to an output buffer (not shown).
However, the related art memory test circuit has various disadvantages. For example, due to the high integration in the related art memory test circuit, a satisfactory throughput of the test process can be achieved only when more address comparisons are carried out. Hence, additional main amps are necessary for the test mode in the memory test circuit. This increases the chip size and reduces the process speed.
Further, the comparison of numerous addresses leads to a decrease of data fault coverage, which causes a problem that failures found by the memory test circuit cannot be repaired, or a problem that an additional test using a full address is then required to locate the failure.
SUMMARY OF THE INVENTION
An object of the present -invention is to provide a memory test circuit that substantially obviates one or more of the problems caused by the disadvantages of the related art.
Another object of the present invention is to reduce a test time of a memory array.
Another object of the present invention is to provide a memory test circuit that reduces a test time of a highly integrated memory without providing an additional main amp.
Another object of the present invention is to provide a memory test circuit that divides a memory array into a plurality of even and odd numbered mats and concurrently tests the even or odd numbered mats to reduce test time of the memory array.
To achieve at least the above objects in a whole or in parts, there is provided a memory test circuit having a mat controlling unit for dividing a plurality of mats into even and odd-numbered units and simultaneously controlling the even or odd-numbered mats, a mat switch controlling unit for controlling a plurality of mat switches to be equentially operated, a main amp controlling unit for controlling a plurality of main amps to be sequentially operated and a latch unit for latching data amplified by the plurality of main amps to be simultaneously outputted. By dividing the mats into even and odd-numbered units, the circuit can simultaneously test the even or odd-numbered mats when testing a highly integrated semiconductor memory device.
To further achieve the above objects in a whole or in parts, there is provided a memory test circuit according to the present invention that include a plurality of mats coupled to local input/output lines, a plurality of mat switches that selectively connect or disconnect corresponding ones of the local input/output lines with global input/output lines, wherein the local input/output lines and the global input/output lines transfer information to the plurality of mats or transfer information stored in the mats, a plurality of main amps that amplify data coupled to the global input/output lines, a mat switch controlling circuit that controls the plurality of mat switches, a latch circuit that latches data amplified by the plurality of main amps to be substantially simultaneously outputted, a mat controlling circuit that controls the plurality of mats to be respectively activated according to each mode of a plurality of modes, and a main amp controlling circuit that controls the plurality of main amps to be sequentially operated.
To further achieve the above objects in a whole or in parts, there is provided a memory test circuit having a plurality of cell array mats according to the present invention that includes a mat controller coupled to each of the plurality of mats and responsive to a first address signal and a test mode enable signal, wherein. the mat controller divides the plurality of mats into even and odd-numbered mats, simultaneously enables one of the even and odd-numbered mats, and sequentially couples each of the plurality of mats with a plurality of input/output lines.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5629898 (1997-05-01), Idei et al.
patent: 5691952 (1997-11-01), Sasaki et al.
patent: 5892721 (1999-04-01), Kim
Takashi Ohsawa et al. “A 60-ns 4-Mbit CMOS DRAM With Built-In-Self-Test Function” IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 663-667.
Chung Phung M.
Fleshner & Kim LLP
Hyundai Micro Electronics Co., Ltd.
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