Memory test and setup method

Details Memory test and setup method Memory test and setup method

2011-04-19

2011-04-19

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

Reexamination Certificate

active

07929363

ABSTRACT:
A method of optimizing memory cell write/read is disclosed. The memory cell write/read is optimized by first reading the memory cell data using the normal mode. Next the page latch data that was used to NV (Non-Volatile) write the memory is also read back directly from the page latches. The two data are then compared to verify a successful and optimized memory cell write/read. NV writes and reads are performed with various high voltage parameters and sense amplifier reference settings to arrive at the most optimal one that gives the largest sense window for best write/read reliability. The page latch read mode is also used as a DFT (Design for Test) test mode to check for page latch functionality and page address uniqueness without having to write the memory cell. The page latch is written with logic data and read out directly using the page latch read mode to verify page functionality.

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