Memory systems and methods for translating memory addresses...

Details Memory systems and methods for translating memory addresses... Memory systems and methods for translating memory addresses...

2009-10-27

2011-12-13

Kindred, Alford (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

Reexamination Certificate

active

08078775

ABSTRACT:
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

REFERENCES:
patent: 5906003 (1999-05-01), Runas
patent: 6151239 (2000-11-01), Batra
patent: 6502161 (2002-12-01), Perego et al.
patent: 7272675 (2007-09-01), Paul et al.
patent: 2003/0172243 (2003-09-01), Ripley
patent: 2003/0182519 (2003-09-01), Riesenman et al.
patent: 2004/0186956 (2004-09-01), Perego et al.
patent: WO 2007/002324 (2007-01-01), None
John, Lizy Kurian, “VaWiRAM: A Variable Width Random Access Memory Module,” 1995 IEEE, 9th International Conference on VLSI Design—1996. pp. 219-224.
“FB-DIMM” Fully-Buffered DIMM dated Jul. 4, 2005, Memory Module Manufactures. 3pages.
“JEDEC Standard—DDR2 SDRAM Specification” JESD-2B (Revision of JESD79-2A), JEDEC Solid State Technology Association. Jan. 2005. 112 pages.
“Rambus—Dynamic Point-to-Point Technology.” http://www.rambus.com/products/innovationslicensing/innovations/dpp.asp. Copyright 2005. Downloaded Oct. 12, 2005. 2 pages.
“Introducing FB-DIMM Memory: Birth of Serial RAM?” dated Aug. 24, 2005 Downloaded from http://www.pcstats.com/articleview.cfm?articleid=1812&page=3.6 pages.
Vogt, Pete. “Fully Buffered DIMM (FB-DIMM) Server Memory Architecture: Capacity, Performance, Reliability, and Longevity”, dated Feb. 18, 2004. 33 pages.
U.S. Appl. No. 60/693,631, Rajan, Suresh N.

Affiliated with

Also associated with

Rating

Memory systems and methods for translating memory addresses... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory systems and methods for translating memory addresses..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory systems and methods for translating memory addresses... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4252783