Memory systems and memory access methods

Details Memory systems and memory access methods Memory systems and memory access methods

2007-01-22

2009-02-03

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S033000

Reexamination Certificate

active

07486105

ABSTRACT:
A memory system includes a first memory unit, a transmission bus having an impedance, and a memory controller having a first on-die termination circuit, coupled to the first memory unit through the transmission bus. The first on-die termination circuit matches the impedance of the transmission bus in response to the memory controller writing data to the first memory unit.

REFERENCES:
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6917546 (2005-07-01), Matsui
patent: 2003/0161196 (2003-08-01), Park et al.

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