Memory system with write coalescing

Details Memory system with write coalescing Memory system with write coalescing

2011-03-08

2011-03-08

Rutz, Jared I (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C710S052000

Reexamination Certificate

active

07904640

ABSTRACT:
A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.

REFERENCES:
patent: 6938116 (2005-08-01), Kim et al.
patent: 7408834 (2008-08-01), Conley et al.
patent: 2005/0174849 (2005-08-01), In et al.
patent: 2005/0289291 (2005-12-01), Takahashi
patent: 2006/0149890 (2006-07-01), Gorobets
patent: 2008/0028132 (2008-01-01), Matsuura et al.
patent: 2009/0172308 (2009-07-01), Prins et al.
patent: 2009/0292860 (2009-11-01), Park
patent: 2010/0023695 (2010-01-01), Guthrie et al.
patent: 8 279295 (1996-10-01), None
patent: 3688835 (2005-08-01), None
patent: 2006-11818 (2006-01-01), None
patent: 2007 528079 (2007-10-01), None
patent: 2008-33788 (2008-02-01), None
Hyojun Kim, et al., “BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage”, Proceedings of the 6thUSENIX Conference on File and Storage Technologies (FAST'08), Feb. 29, 2008, pp. 239-252.
Hennessy, John L. et al., “Computer Organization and Design, The Hardware/Software Interface”, Morgan Kaufmann Publishers, Inc., 2ndEdition, pp. 540-541, Aug. 31, 2004).
U.S. Appl. No. 12/551,213, filed Aug. 31, 2009, Kanno, et al.
U.S. Appl. No. 12/529,126, filed Aug. 28, 2009, Yano, et al.
U.S. Appl. No. 12/529,139, filed Aug. 28, 2009, Yano, et al.
U.S. Appl. No. 12/529,127, filed Aug. 28, 2009, Yano, et al.
U.S. Appl. No. 12/529,192, filed Aug. 31, 2009, Yano, et al.
U.S. Appl. No. 12/529,282, filed Aug. 31, 2009, Hida, et al.
U.S. Appl. No. 12/552,330, filed Sep. 2, 2009, Yano, et al.
U.S. Appl. No. 12/552,422, filed Sep. 2, 2009, Kitsunai,et al.
U.S. Appl. No. 12/566,236, filed Sep. 24, 2009, Yano, et al.
U.S. Appl. No. 12/529,228, filed Aug. 31, 2009, Yano, et al.
U.S. Appl. No. 12/563,856, filed Sep. 21, 2009, Yano, et al.

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