Memory system with write buffer, prefetch and internal caches

Details Memory system with write buffer, prefetch and internal caches Memory system with write buffer, prefetch and internal caches

1990-08-06

1998-11-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711125, 711126, 711128, G06F 1208

Patent

active

058359451

ABSTRACT:
A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

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