Memory system with sector buffers

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C711S102000

Reexamination Certificate

active

08006031

ABSTRACT:
The invention relates to a memory system which is connected to a host system by means of a host bus (HB). Said system contains a memory controller (FC) having an internal memory (IR) and flash memory chips (F1. . . Fn) which are organised in individually deletable memory blocks. Said blocks contain a plurality of writeable and readable memory sectors, and the sectors are divided into sector sections which are secured by an ECC-word. The sectors are temporarily stored in the alternating sector buffers (SB1, SB2) in order to communicate with the host system and are transmitted between the sector buffers (SB1, SB2) and the flash memory chips (F1. . . Fn), by means of a direct-flash-access-unit (DFA), without having to be temporarily stored in the internal memory (IR) of the memory controller (FC).

REFERENCES:
patent: 5630093 (1997-05-01), Holzhammer et al.
patent: 5822251 (1998-10-01), Bruce et al.
patent: 6421274 (2002-07-01), Yoshimura
patent: 6643730 (2003-11-01), Okumura et al.
patent: 6778436 (2004-08-01), Piau et al.
patent: 2002/0097594 (2002-07-01), Bruce et al.
patent: 2002/0124129 (2002-09-01), Zilberman
patent: 2004/0049627 (2004-03-01), Piau et al.
patent: 2010/0054069 (2010-03-01), Shiota et al.
patent: 0550241 (1993-07-01), None

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