Memory system with row clamping arrangement

Details Memory system with row clamping arrangement Memory system with row clamping arrangement

1978-09-15

1979-09-18

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365155, 307DIG3, G11C 700, G11C 1140

Patent

active

041685393

ABSTRACT:
A memory system of an array of memory elements arranged in an electrical matrix of rows and columns. Each memory element comprises a bistable circuit of two bipolar transistors. Holding current flows through the on transistor of each memory element of a row from a common current source to a common line. When a memory element is switched so that is transistors reverse operating conditions, the holding current flow through the memory element is diverted during the transition. A clamping arrangement of a transistor and associated resistance is connected between the common current source and the common line of each row. When all of the memory elements of a row are switched at the same time the clamping arrangement provides an alternative controlled current path for the diverted holding currents.

REFERENCES:
patent: 4099070 (1978-07-01), Reinert
Blount et al., DI-Istor Speed-Up Word Drive With Resistor Word Bottom, IBM Tech. Disc. Bul., vol. 14, No. 6, 11/71, pp. 1734-1735.

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