Memory system with multiplexed input-output port and memory mapp

Details Memory system with multiplexed input-output port and memory mapp Memory system with multiplexed input-output port and memory mapp

1996-04-24

1998-11-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

711202, G06F 1200

Patent

active

058359656

ABSTRACT:
A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

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