Memory system with adaptable redundancy

Details Memory system with adaptable redundancy Memory system with adaptable redundancy

1992-03-09

1994-10-25

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

053595637

ABSTRACT:
A memory system with adaptable redundancy comprises address decoding means (200) for the selection of one of the rows R.sub.1 to R.sub.2 (n+1) in the memory array, according to the binary value of address A.sub.0, A.sub.1, . . . A.sub.nn incoming on bus 102. Block 200 comprises 2.sup.(n+1) blocks 201 being able to drive an activation signal on leads R.sub.1 to R.sub.2 (n+1), and having an output connected to a lead 206.
Block 205 is able to drive an activation signal on lead RR according to signals present on leads 107 and 206, so as to select redundant row RR.sub.1 without the use of a redundant address decoder.

REFERENCES:
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 4635232 (1987-01-01), Iwahashi et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4935899 (1990-06-01), Morigami
Redundant/Normal Clock Generation for Redundant Word Line Addressing, IBM TDB, vol. 32, No. 8A, Jan. 1990, pp. 75-76.

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