Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1997-03-12
1999-02-16
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711105, 711154, 711155, 711119, G06F 1202
Patent
active
058731229
ABSTRACT:
A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
REFERENCES:
"Hitachi IC Memory Data Book 3 (DRAM, DRAM Modules)", pp. 445-464.
"Hot Chips IV", pp. 4.2.2-4.2.12, Aug. 1992, Stanford University.
HM 5241605 series 131072-word.times.16-bit.times.2-bank Synchronous Dynamic RAM Feb. 20, 1994.
Hayashi Nobuyuki
Hiratsuka Noriharu
Nishii Osamu
Okada Tetsuhiko
Takeda Hiroshi
Chan Eddie P.
Hitachi , Ltd.
Nguyen T. V.
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