Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-02-03
2003-01-14
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S103000, C365S185110, C365S185290, C365S230060
Reexamination Certificate
active
06507885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to a memory system having an array of memory cells (e.g., a flash memory system which includes an array of flash memory cells and emulates a magnetic disk drive). More specifically, the invention pertains to a method and system for simultaneously selecting two or more blocks of cells of a memory cell array, so that data can be written to (or read from) the selected blocks simultaneously.
2. Description of Related Art
It is conventional to implement a memory system as an integrated circuit which includes an array of flash memory cells (or other non-volatile memory cells) and circuitry for independently erasing selected blocks of the cells, programming selected ones of the cells (i.e., writing data to selected ones of the cells), and reading data from selected ones of the cells.
FIG. 1
is a simplified block diagram of a flash memory system (flash memory system
3
) which is designed to emulate a magnetic disk drive system. Although system
3
can be implemented as a single integrated circuit, it is not necessarily implemented as a single integrated circuit, and the following description of system
3
will not assume that it is an integrated circuit.
As shown in
FIG. 1
, system
3
includes memory cell array
16
which comprises rows and columns of flash memory cells (each row of cells connected along a different wordline, and each column of cells connected along a different bitline or bit line), predecoding circuit or predecoder
49
, row decoder circuit (X address decoder)
12
, and Y-decoder circuit
13
. Row decoder circuit
12
includes two physically separated sets of wordline drivers: a first set of wordline drivers
12
A (positioned physically nearest to the bitline on the left side of array
16
), and a second set of wordline drivers
12
B (positioned physically nearest to the bitline on the right side of array
16
).
The wordlines of array
16
are driven by two physically separated sets of wordline drivers: a first set of wordline drivers
12
A (positioned physically nearest to bitline BL
0
on the left side of the array), and a second set of wordline drivers
12
B (positioned physically nearest to bitline BLN on the right side of the array). Each of the control gates of each of the cells connected along the even-numbered wordlines (wordlines WL
0
, WL
2
, etc.) is driven by a driver circuit within set
12
A (i.e., each driver circuit within set
12
A asserts an appropriate control voltage to each such control gate). Each of the control gates of each of the cells connected along the odd-numbered wordlines (wordlines WL
1
, WL
3
, etc.) is driven by a driver circuit within set
12
B.
The drivers comprising set
12
A are positioned along the left side of array
16
and are connected to the control gates of each of the flash memory cells of array
16
that are connected along the even-numbered wordlines of array
16
, and the drivers comprising set
12
B are positioned along the right side of array
16
and connected to the control gates of each of the cells connected along the odd-numbered wordlines of array
16
. This arrangement of drivers
12
A and
12
B provides most efficient use of the area of system
3
, allowing system
3
to be implemented with a smaller overall size than if all of drivers
12
A and
12
B were positioned on the same side of array
16
.
In variations on system
3
, array
16
is implemented so that each of two or more integrated circuits contains a different portion of array
16
.
To enable a conventional flash memory system such as system
3
to implement the present invention, its predecoder circuit would need to be modified to become capable of asserting multiblock selection bits, so that in response to each set of multiblock selection bits, the system is capable of simultaneously selecting two or more selected blocks of cells of array
16
(in a manner to be explained below).
For convenience throughout this disclosure, we use the following notation to describe address bits. “A(Y:Z)” denotes a set of (Y−(Z−1)) address bits, consisting of binary bits A
y
, A
y−1
, . . . A
z+1
, and A
z
. For example, A(
8
:
0
) denotes the following nine address bits: A
8
, A
7
, A
6
, A
5
, A
4
, A
3
, A
2
, A
1
, and A
0
.
With reference again to
FIG. 1
, memory system
3
also includes control engine (or “controller”)
29
, output buffer
10
, input buffer
11
, and host interface
4
. Host interface
4
asserts data from output buffer
10
(e.g., data read from array
16
) to an external device (not shown), and asserts input data from the external device to input buffer
11
(so that such input data can be written to array
16
).
Alternatively, where host interface
4
includes input and output data buffers, buffers
10
and
11
can be eliminated and the data buffers within interface
4
used in place of them.
Host interface
4
also includes an address buffer for receiving external address bits from the external device, and is configured to send buffered address bits (including bits identifying cylinder, head, and sector addresses) to controller
29
in response to receiving external address bits from the external device. Host interface
4
also generates control signals in response to external control signals received from the external device and asserts the control signals to controller
29
.
Where the external device is a host processor having a standard disk operating system (DOS) with a Personal Computer Memory Card International Association (PCMCIA)-AT Attachment (ATA) interface for communicating with a magnetic disk drive system, interface
4
should also comply with the PCMCIA-ATA standard so that it can communicate with the standard PCMCIA-ATA interface of the external device.
In response to receiving the above-mentioned adress bits (including bits identifying cylinder, head, and sector addresses) from interface
4
, control engine
29
generates translated address bits A(
22
:
0
) and asserts the translated address bits to predecoding circuit (“predecoder”)
49
. In response to the translated address bits (and to control signals from control engine
29
), predecoder
49
asserts wordline and bitline selection bits to row decoder
12
and Y decoder circuit
13
. In response to the selection bits (and to below-discussed address bit AX and control signals from control engine
29
), circuits
12
and
13
select cells of array
16
to which data is to be written or from which data is to be read.
For example, where address bits A
18
, A
17
, and A
16
determine the erase block of the target cells (and where array
16
includes eight erase blocks per main block), predecoder generates an 8-bit set of selection bits XC(
7
:
0
) (sometimes referred to as “erase block enable” bits) as follows, in response to each set of address bits A(
18
:
16
):
A18
A17
A16
XC (7:0)
0
0
0
00000001
0
0
1
00000010
0
1
0
00000100
0
1
1
00001000
1
0
0
00010000
1
0
1
00100000
1
1
0
01000000
1
1
1
10000000
The single bit having value “one” in each set of selection bits XC(
7
:
0
) selects a different erase block (within a single selected main block). Bits XC(
7
:
0
) consist of XC
0
which selects the first erase block, XC
1
which selects the second erase block, XC
2
which selects the third erase block, XC
3
which selects the fourth erase block, XC
4
which selects the fifth erase block, XC
5
which selects the sixth erase block, XC
6
which selects the seventh erase block, and XC
7
which selects the eighth erase block.
Each of the cells (storage locations) of memory array circuit
16
is indexed by a row index (an “X” index determined by decoder circuit
12
) and a column index (a “Y” index determined by Y decoder circuit
13
). Each column of cells of array
16
comprises “X” memory cells (where X is an integer), with each cell implemented by a single floating-gate N-channel transistor.
In one embodiment in which array
16
includes ten main blocks (
16
A through
16
J), each main block has 1024 rows of cells, each row has 4352 cells (and thus there are 4352 column
Adsitt Mathew L.
Chevallier Christophe J.
Lakhani Vinod C.
Gossage Glenn
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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