Memory system including CMOS memory cells and bipolar sensing ci

Details Memory system including CMOS memory cells and bipolar sensing ci Memory system including CMOS memory cells and bipolar sensing ci

1989-06-30

1993-01-12

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Differential sensing

365177, 365179, 36518909, 36523005, G11C 706, G11C 11407

Patent

active

051795388

ABSTRACT:
A memory system (10) is disclosed including a memory array (14), decoder circuit (16), and sensing circuit (17). The memory array includes a plurality of two-port CMOS memory cells (42) arranged in columns and rows that are selectively addressed by the decoder circuit. The bipolar sensing circuit responds to data stored in an addressed memory cell in the following manner. A column decoder (28) in the decoder circuit provides information to a source select multiplexer (30) and a column read access port (18) to selectively couple information stored in the memory cell to an output stage (20). At the output stage a comparison is made between the stored data and a reference voltage provided by a threshold circuit (38) to produce an output indicating the sensed level. The memory cells are preferably asymmetrically designed for hysteretic operation. The resultant bipolar/CMOS memory system advantageously combines the attributes of high density, high speed, and low power consumption.

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