Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1996-12-23
1998-07-21
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Data refresh
365211, 365149, G11C 700
Patent
active
057843287
ABSTRACT:
A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.
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Irrinki V. Swamy
Kapoor Ashok
Leung Raymond
Owens Alex
Wik Thomas R.
Kivlin B. Noel
LSI Logic Corporation
Nelms David C.
Nguyen Hien
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