Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-06-22
2003-04-29
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S005000, C711S157000, C365S189050, C365S193000, C365S230030
Reexamination Certificate
active
06557071
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to accessing a memory array in a computer system. More particularly, the present invention is directed to accessing a memory array in a computer system using a data strobe.
BACKGROUND OF THE INVENTION
Computer systems require a large amount of memory in order to store programs and data. One type of memory common to virtually all computer systems is dynamic random access memory (“DRAM”).
When accessing DRAM, a row address strobe (“RAS”) must first be asserted, and then a column address strobe (“CAS”) is asserted. Since DRAM is asynchronous, data cannot be read from or written into DRAM until some delay time after the CAS asserted, in order to allow the DRAM sufficient time to react to the CAS. This delay time reduces the access speed of the DRAM.
Another delay that reduces the access speed of DRAM is the time for the RAS and CAS signals to physically reach the DRAM after they are generated. In a typical desktop personal computer, the total DRAM might occupy 1-2 dual in-line memory module (“DIMM”) slots, and the signal delay is minimal. However, in large multiprocessor computer servers, the amount of required DRAM can sometimes occupy 32 or more DIMM slots. Because of the large number of memory boards in these systems, the longest trace lengths between the device generating the RAS and CAS signals and the DRAMs must be increased to reach all of the DRAMs. The increased trace length, because of added capacitance, further increases the time for the RAS and CAS signals to reach the DRAMs, therefore further reducing the access speed of the DRAMs.
Based on the foregoing, there is a need for a method and apparatus to increase the access speed of DRAM, regardless of the amount of DRAM in a computer system.
SUMMARY OF THE INVENTION
One embodiment of the present invention is a memory subsystem for a computer system. The memory subsystem includes a memory controller that has a data strobe generator. The memory subsystem further includes a DRAM array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array.
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Pawlowski Stephen S.
Stolt Patrick F.
Gossage Glenn
Intel Corporation
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