Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-06-24
2001-08-07
Bragdon, Reginald G. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S185010, C365S185020, C365S185240, C365S189011
Reexamination Certificate
active
06272586
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory systems, and in particular to memory systems having programmable control parameters which control the operation of the memory and which can be reprogrammed after the memory system has been fabricated.
2. Background Art
Integrated circuit memory systems have been developed having very large storage capacities. Although attempts have been made to carefully control the fabrication of these memory systems so as to increase the yield, there invariably will be differences in memory system characteristics even for memory systems that utilize the same design. These differences in characteristics are attributable to many factors but the majority of differences are due to processing variations. Thus, memory systems taken from one semiconductor wafer may differ significantly from those taken from other wafers.
It is usually not possible to fully characterize a memory system until it is completely fabricated. At that point, it is not possible to modify the memory system to take into account the characteristics of the memory. By way of example, in a flash memory system it is possible to electrically program, read and erase the flash cells. The logic state of the cell is set by either programming or erasing the cell, with programming and erasing functioning to alter the threshold voltage of the cell. When the cell is read, the threshold voltage of the cell is determined in order to establish the logic state of the cell. However, the characteristics of the flash cell, such as the exact manner in which the flash cells respond to programming pulses or erase pulses, are not easily ascertained. The threshold voltage of the cell of one memory system may change one amount after a single programming pulse is applied and a cell of a another supposedly identical memory system may change a different amount after the same programming pulse is applied to it.
In order to accommodate these variations in memory system characteristics, it is typically necessary to design the system assuming worst case conditions. In that event, the overall performance of the system will almost by necessity be reduced.
Also, many processor systems which operate with an associated memory require a particular memory configuration to operate properly. By way of example, some systems require a word length of eight bits and some require sixteen bits. There are conventional memory systems available which permit the end user to control the word size to some degree. However, this somewhat increases the complexity imposed upon the end user of the memory since the end user must provide the necessary signals to the memory for controlling the word length. As a further example, most processor systems look to a certain portion of a memory for boot data at power on. Such boot data is necessary for the processor to function in system. The processor will be implemented to expect the boot data to be at a specific memory address. Some processors expect the boot data to be at the memory low addresses (bottom boot) and some processors expect the boot data to be at the memory high addresses (top boot).
In order to provide capabilities for different types of processor systems, it is possible to produce a different memory system for each application. However, it is always desirable to limit the number of different memory types which must be manufactured.
It would be desirable to have a memory system where the system can be fully characterized after fabrication and wherein certain operating parameters can then be permanently adjusted so as to provide a memory system that is optimized to take into account the particular characteristics of the system. It would also be desirable to provide the capability for modifying the configuration of a memory system after fabrication so as to reduce the number of different types of memories which must be fabricated. The present invention provides these features and other improved features as will become apparent to those skilled in the art upon a reading of the Detailed Description of the Invention together with the drawings.
SUMMARY OF THE INVENTION
A memory system capable of being configured for optimum operation after fabrication is disclosed. The system includes an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control means is included for controlling memory operations, with the memory operations including programming the memory cells; reading the memory cells and preferably erasing the cells.
The system further includes a plurality of non-volatile data storage units, with the data storage units storing control parameter data used by the control means for controlling the memory operations. Such control parameters can include parameters for adjusting the magnitude and duration of voltage pulses applied to the memory for carrying out programming and erasing operations. They can also include parameters for controlling the length (number of bits) of the words read out and programmed into the memory. In addition, the control parameters can include parameters for controlling the addressing of the memory system so that, for example, an external address can be altered so that the actual address applied to the memory is inverted.
The memory system includes mode means for switching the memory system between a normal operating mode where the cells of the array may be programmed and read and an alternative mode where the control parameter data in the data storage units may be modified. Preferably, the alternative mode is one which is entered only by way of application of signals to the terminals of the memory system of a greater magnitude than used in normal memory operation so that accidental entry into the alterative mode is reduced. Once the memory system has been fabricated it is then possible to characterize the memory and select values for the control parameters for optimizing memory system operation, with these parameters being programmed into the non-volatile data storage units.
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Briner Michael S.
Chevallier Christophe J.
Rinerson Darrell D.
Roohparvar Frankie F.
Bragdon Reginald G.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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