Memory system having multiple reading and writing ports

Details Memory system having multiple reading and writing ports Memory system having multiple reading and writing ports

1998-06-17

1999-09-28

Phan, Trong

Static information storage and retrieval

Addressing

Multiple port access

36523008, 36518905, G11C 800, G11C 1604

Patent

active

059599316

ABSTRACT:
A multi-port type semiconductor memory device which can reduce the number of bit lines, the size of a memory, and the power consumption, wherein write and read operations are carried out by using a pair of bit lines in common; at the time of a write operation the levels of the bit lines are determined in response to write data, and the levels of first and second memory nodes are determined via a writing port WPT and maintained by latch circuits; at the time of a read operation, in response to the levels of the first and the second memory nodes, the levels of the bit lines are determined via a first and a second reading ports and read data is output in accordance with the levels of the bit lines by a sense amplifier.

REFERENCES:
patent: 4933899 (1990-06-01), Gibbs
patent: 5260908 (1993-11-01), Ueno
patent: 5790461 (1998-08-01), Holst

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