Memory system having high-speed row block and column redundancy

Details Memory system having high-speed row block and column redundancy Memory system having high-speed row block and column redundancy

2007-03-29

2009-02-24

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

07495977

ABSTRACT:
A high-speed redundancy circuit having redundant rows/blocks for replacing defective rows, columns and blocks. For row redundancy, an off-pitch encoder in conjunction with row control circuitry is used to disable defective rows while enabling non-defective rows. An off-pitch fuse is blown to enable redundant rows for a particular sub-array. Therefore, the enabled redundant row replaces the disabled defective row. For column/block redundancy, an encoder is used where appropriate off-pitch fuses are blown to enable the appropriate redundant blocks. Unlike row redundancy, the defective columns/blocks are not disabled. Instead when redundant blocks are enabled, the column/block control unit detects whether to transfer data to/from the redundant block/columns or block/columns corresponding to the defective columns. As a result of using off-pitch fuses the die size is reduced. Moreover, speed improves because complex circuitry is no longer required to disable defective columns/blocks and because enabling/disabling of rows occurs during an equalization period.

REFERENCES:
patent: 5224073 (1993-06-01), Nakayama
patent: 6055204 (2000-04-01), Bosshart
patent: 6275406 (2001-08-01), Gibson et al.
patent: 6385071 (2002-05-01), Chai et al.

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