Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2003-12-01
2008-08-19
Nguyen, Hiep T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
Reexamination Certificate
active
07415579
ABSTRACT:
A memory system is provided which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by operational memory commands that use logical memory sector numbers. The inventive system is characterized by an arbitration among the memory controllers so that for any memory operation requested by the host system (HS) the memory controller affected with respect to a range of logical memory sector numbers takes over the bus for communication with the host system.
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Baumhof Christoph
Kühne Reinhard
Browdy and Neimark
Hyperstone GmbH
Nguyen Hiep T
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