Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-11-08
2005-11-08
Sparks, Donald (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S140000, C711S150000, C711S151000, C711S152000, C711S158000, C711S168000, C711S210000, C710S022000, C710S039000, C710S040000, C709S241000
Reexamination Certificate
active
06963962
ABSTRACT:
A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.
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Chinnakonda Murali S.
Ramagopal Hebbalalu S.
Tran Thang M.
Analog Devices Inc.
Sparks Donald
Truong Bao Q
Wolf Greenfield & Sacks P.C.
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