Memory system for ANDing data bits along columns of an inverted

Details Memory system for ANDing data bits along columns of an inverted Memory system for ANDing data bits along columns of an inverted

1991-01-10

1992-07-28

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

36518905, 3652385, 365 63, 395164, 395425, 340799, 340803, G11C 700, G11C 1200, G06F 1562

Patent

active

051345820

ABSTRACT:
A memory system is provided with two data buffers, respectively, in the row and column directions of a memory array. The system is capable of operating either one of the two data buffers as input/output buffers in accordance with reading or writing operations on the contents of the memory array. Outputs from the memory array are inverted to form an inverted array. All bits along respective columns of the array are ANDed together to obtain an ANDed bit value for each column of the inverted array.

REFERENCES:
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patent: 4559618 (1985-12-01), Houseman et al.
patent: 4667308 (1987-05-01), Hayes et al.
patent: 4670846 (1987-06-01), Laws
patent: 4740927 (1988-04-01), Baker et al.
patent: 4742474 (1988-05-01), Knierim
patent: 4755810 (1988-07-01), Knierim

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