Memory system comprising a semiconductor memory

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S233100, C365S233500

Reexamination Certificate

active

10735250

ABSTRACT:
A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

REFERENCES:
patent: 5822244 (1998-10-01), Hansen et al.
patent: 5978891 (1999-11-01), Takeda
patent: 6169423 (2001-01-01), Campardo et al.
patent: 6237104 (2001-05-01), Micheloni et al.
patent: 6385078 (2002-05-01), Jeon
patent: 6748464 (2004-06-01), Mori et al.

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