Memory system capable of reducing timing skew between clock sign

Details Memory system capable of reducing timing skew between clock sign Memory system capable of reducing timing skew between clock sign

1997-03-10

1999-07-20

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711154, 395878, 395306, G06F 1316

Patent

active

059268379

ABSTRACT:
A memory system includes a data bus which is folded, a clock signal line extending in parallel with the data bus for transferring a clock signal, memories connected to the data bus and the clock signal line, and memories controller for controlling the memories, wherein the memory controller generates a clock signal to supply it to one end of the clock signal line, and is responsive to a clock signal input from another end of the clock signal line to receive data output from the memory from one end of the data bus.

REFERENCES:
patent: 4663758 (1987-05-01), Lambarelli et al.
patent: 5210750 (1993-05-01), Nassehi et al.
patent: 5268656 (1993-12-01), Muscavage
patent: 5432823 (1995-07-01), Gasbarro et al.
"A 32-bank IGb DRAM with IGB/s Bandwidth", Digest of Technical Press, pp. 378-379, ISSC/Feb. 10, 1996/Buena Vista/3:45PM.

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