Memory system architecture

Details Memory system architecture Memory system architecture

1997-10-02

2001-05-01

Ellis, Kevin L. (Department: 2751)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

Reexamination Certificate

active

06226732

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory systems for computers and other data processing systems. More specifically, the present invention includes a memory architecture having one or more virtually addressable segments and one or more physically addressable segments.
BACKGROUND OF THE INVENTION
Computers and other data processing systems generally include some form of memory system. Typically these memory systems are organized as a sequence of memory locations with each location storing a fixed number of memory bits. Each memory location is accessed using its own numeric address. Thus, the first memory location has a numeric address of zero. The second has an address of one, and so on. These numeric addresses are known as physical addresses.
The use of physical addresses (physical addressing) is a simple and fast method for addressing the contents of a memory system. Consequently, physical addressing is used in a wide range of computer system types. For example, cost is a paramount issue in many embedded computers. Thus, the simplicity of physical addressing is often appropriate for these computers. In computer systems used for digital signal processing, speed of execution may be paramount. As a result, physical addressing is often appropriate for these computer systems as well.
Virtual addressing is a technique that builds onto and extends the physical addressing model. In virtual addressing, memory locations are accessed using numeric addresses known as virtual addresses. The virtual addresses are then translated or mapped into physical addresses to perform the requested access. The mappings between virtual addresses and physical addresses are established at runtime, generally on a per-process basis. Thus, each process will have its own, unique mapping between virtual addresses and physical addresses. The per-process mapping between virtual addresses and physical addresses may also be dynamic. Thus, the physical address referenced by a virtual address may change over the life a process.
The use of virtual addresses has a number of advantages. For example, using virtual addresses a set of processes be loaded into the same memory system. Each process is then given a range of virtual addresses that starts at zero. Each processes' range of virtual addresses is then mapped to a different set of physical addresses. In this way, a single memory system is shared between the set of processes.
Virtual addressing may also be used to provide systems where the range of virtual addresses exceeds the range of physical addresses. Typically, this is accomplished by dividing a process' range of virtual addresses into a series of regions or pages. The pages of memory are stored within a secondary storage system such as a disk drive. When a process needs a particular page, the page is moved into the memory system. As the page is moved into the memory system, the process' mapping between virtual addresses and physical addresses is updated to reflect the physical address of the page within the memory system. Importantly, by storing pages within a secondary storage system, it becomes possible for number of pages to exceed the number of locations available within the memory system (i.e., each process may have more pages than will ‘fit’ within the memory system). In this way, it is possible to create systems where the range of virtual addresses exceeds the range of physical addresses.
The addition of virtual addressing greatly enhances the flexibility of memory systems. Unfortunately, this increase in flexibility is typically achieved by slowing down the speed of the memory system. This decrease in speed is attributable to the time required to translate each virtual address to its corresponding physical address. The translation time may be partially masked by providing a cache for recently translated virtual addresses. Still, it is generally the case that virtual addressing cannot match the speed of physical addressing.
The difference in speed, complexity and flexibility provided by virtual addressing and physical addressing has generally caused designers of computer systems to choose between the two methods. Thus, general purpose computers are typically designed to use virtual addresses. Specialized computers, such as digital signal processing systems, and embedded systems are typically designed to use physical addressing.
Increasingly, however, there is a need for memory systems that provide the speed of physical addressing and the flexibility of virtual addressing. For example, in highly integrated systems, like advanced handheld computers, there is a need for a range of different processes. Some of these processes are akin to the processes typically executed by general purpose computers. Other processes perform digital signal processing or embedded tasks. As a result, these integrated computers have a need for the speed of physical addressing and the flexibility of virtual addressing. Thus, a need exists for memory systems that combine these advantages.
SUMMARY OF THE INVENTION
The present invention is directed to a memory system including memory that is accessible using physical addresses and memory that is accessible using virtual addressees. The portions of memory accessible using physical addresses exhibit the advantages of speed and relative simplicity. The portions of memory accessible using virtual addressing exhibit advantages such as flexibility. The invention includes a memory architecture having a virtual memory system and a physical memory system. The virtual memory system and physical memory system may be connected to a common address bus and a control bus. The virtual memory system includes a memory management unit (MMU) that translates virtual addresses to physical addresses. The virtual memory system also includes a cache memory unit. The physical memory system includes an auxiliary memory array and a main memory array.
The memory architecture includes several modes of operation. For one such mode of operation, the control bus is configured to indicate that the auxiliary memory array is disabled. A virtual address is then placed on the address bus. The MMU receives the virtual address and translates the virtual address to its corresponding physical address. The virtual memory unit then uses the physical addresses to access the correct memory location in the cache memory unit or the main memory array.
For a second mode of operation, the control bus is configured to indicate that the auxiliary memory array is enabled. A virtual address is then placed on the address bus. The MMU receives the virtual address and compares it to a range of shadowed addresses. If the virtual address is within the range of shadowed addresses, the MMU uses the virtual addresses to access the correct memory location in the auxiliary memory array. Alternatively, if the virtual address is not within the range of shadowed addresses, the virtual memory system performs the access as previously described.
The present invention may also include third and fourth modes of operation where the address translation within the MMU is disabled. In the third mode, the virtual memory system is disabled. In this mode, all memory addresses are physical addresses and all memory addresses are located in the main memory array. In the fourth mode of operation, all memory addresses are once again physical addresses. For the fourth mode, however, a range of shadowed addresses are located in the auxiliary memory array. The present invention may also include a fifth mode of operation where the virtual memory system and main memory array are disabled and the auxiliary memory array is active.
The combination of the virtual memory system and the physical memory system provides an environment where applications that require maximum execution speed can be accommodated while still maintaining the flexibility of a virtual memory architecture.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art fr

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