Memory system and method using stacked memory device dice,...

Details Memory system and method using stacked memory device dice,... Memory system and method using stacked memory device dice,...

2011-08-30

2011-08-30

Le, Vu A (Department: 2824)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S819000

Reexamination Certificate

active

08010866

ABSTRACT:
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

REFERENCES:
patent: 5960008 (1999-09-01), Osawa et al.
patent: 6052329 (2000-04-01), Nishino et al.
patent: 6122688 (2000-09-01), Barth et al.
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6363017 (2002-03-01), Polney
patent: 6401213 (2002-06-01), Jeddeloh
patent: 6519194 (2003-02-01), Tsujino et al.
patent: 6574626 (2003-06-01), Regelman et al.
patent: 6882304 (2005-04-01), Winter et al.
patent: 6907555 (2005-06-01), Nomura et al.
patent: 7058865 (2006-06-01), Mori et al.
patent: 7135905 (2006-11-01), Teo et al.
patent: 7149134 (2006-12-01), Streif et al.
patent: 7168005 (2007-01-01), Adams et al.
patent: 7184916 (2007-02-01), Resnick et al.
patent: 7197101 (2007-03-01), Glenn et al.
patent: 7203259 (2007-04-01), Glenn et al.
patent: 7389375 (2008-06-01), Gower et al.
patent: 7489743 (2009-02-01), Koh et al.
patent: 7567476 (2009-07-01), Ishikawa
patent: 7710144 (2010-05-01), Dreps et al.
patent: 2002/0004893 (2002-01-01), Chang
patent: 2002/0097613 (2002-07-01), Raynham
patent: 2002/0130687 (2002-09-01), Duesman
patent: 2002/0138688 (2002-09-01), Hsu et al.
patent: 2003/0041299 (2003-02-01), Kanazawa et al.
patent: 2004/0073767 (2004-04-01), Johnson et al.
patent: 2004/0168101 (2004-08-01), Kubo
patent: 2004/0206982 (2004-10-01), Lee et al.
patent: 2004/0237023 (2004-11-01), Takahashi et al.
patent: 2004/0246026 (2004-12-01), Wang et al.
patent: 2005/0091471 (2005-04-01), Conner et al.
patent: 2005/0157560 (2005-07-01), Hosono et al.
patent: 2006/0126369 (2006-06-01), Raghuram
patent: 2006/0245291 (2006-11-01), Sakaitani
patent: 2006/0273455 (2006-12-01), Williams et al.
patent: 2007/0271424 (2007-11-01), Lee et al.
patent: 2008/0147897 (2008-06-01), Talbot
patent: 2009/0006775 (2009-01-01), Bartley et al.
patent: 2009/0016130 (2009-01-01), Menke et al.
patent: 2009/0196093 (2009-08-01), Happ et al.
patent: 2009/0300314 (2009-12-01), LaBerge et al.
patent: 2009/0300444 (2009-12-01), Jeddleoh
patent: 2010/0005217 (2010-01-01), Jeddeloh
patent: 2010/0005376 (2010-01-01), LaBerge et al.
patent: 2010/0042889 (2010-02-01), Hargan
Related U.S. Appl. No. 12/970,086, filed Dec. 16, 2010, entitled “Phase Interpolators and Push-Pull Buffers”.

Affiliated with

Also associated with

Rating

Memory system and method using stacked memory device dice,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory system and method using stacked memory device dice,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory system and method using stacked memory device dice,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2776395