Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-09-21
2003-06-10
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S147000, C711S154000, C710S058000, C710S107000, C710S317000
Reexamination Certificate
active
06578126
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory system (and method of using same) wherein a novel memory operation protocol may be used to facilitate the execution of memory operations.
BACKGROUND OF THE INVENTION
Network computer systems generally include a plurality of geographically separated or distributed computer nodes that are configured to communicate with each other via, and are interconnected by, one or more network communications media. One conventional type of network computer system includes a network storage subsystem that is configured to provide a centralized location in the network at which to store, and from which to retrieve data. Advantageously, by using such a storage subsystem in the network, many of the network's data storage management and control functions may be centralized at the subsystem, instead of being distributed among the network nodes.
One type of conventional network storage subsystem, manufactured and sold by the Assignee of the subject application (hereinafter “Assignee”) under the trade name Symmetrix™ (hereinafter referred to as the “Assignee's conventional storage system”), includes a plurality of disk mass storage devices configured as one or more redundant arrays of independent (or inexpensive) disks (RAID). The disk devices are controlled by disk controllers (commonly referred to as “back end” controllers/directors) that store user data in, and retrieve user data from a shared cache memory resource in the subsystem. A plurality of host controllers (commonly referred to as “front end” controllers/directors) may also store user data in, and retrieve user data from, the shared cache memory resource. The disk controllers are coupled to respective disk adapters that, among other things, interface the disk controllers to the disk devices. Similarly, the host controllers are coupled to respective host channel adapters that, among other things, interface the host controllers via channel input/output (I/O) ports to the network communications channels (e.g., Small Computer Systems Interface (SCSI), Enterprise Systems Connection (ESCON), and/or Fibre Channel (FC) based communications channels) that couple the storage subsystem to computer nodes in the computer network external to the subsystem (commonly termed “host” computer nodes or “hosts”).
In the Assignee's conventional storage system, the shared cache memory resource may comprise a plurality of memory circuit boards that may be coupled to an electrical backplane in the storage system. The cache memory resource is a semiconductor memory, as distinguished from the disk storage devices also comprised in the Assignee's conventional storage system, and each of the memory boards comprising the cache memory resource may be populated with, among other things, relatively high-speed synchronous dynamic random access memory (SDRAM) integrated circuit (IC) devices for storing the user data. The shared cache memory resource may be segmented into a multiplicity of cache memory regions. Each of the regions may, in turn, be segmented into a plurality of memory segments.
Computer programs may include instruction loops comprising respective sets of instructions that may be repetitively executed in a plurality of respective iterations. The execution of an iteration of a set of loop instructions may be conditioned upon whether a respective control variable value (e.g., a loop counter value) stored in the cache memory resource satisfies one or more predetermined arithmetic and/or logical relationships involving that value. Additionally, each time a determination is made as to whether to execute an iteration of a set of loop instructions, it is typically necessary to change (e.g., increment/decrement) the stored value of the associated control variable.
When a determination is to be made as to whether such a control variable value satisfies an associated predetermined relationship, a set of related operations (hereinafter termed “the related operations”) may be performed in the Assignee's conventional storage system. The set of related operations may include (1) retrieving (e.g., to a host or disk controller) from the cache memory system the value of that control variable that is presently stored in the cache memory resource (hereinafter termed “the present control variable value”), (2) performing one or more arithmetic and/or logical calculations using the retrieved control variable value for the purpose of determining whether the present control variable value satisfies the associated predetermined relationship, and (3) overwriting the present control variable value stored in the cache memory resource with an updated control variable value.
The cache memory resource in the Assignee's conventional storage system is configured to carry out relatively simple read-modify-write operations, based upon commands received from a host or disk controller, that may be used to facilitate at least some of these related operations. For example, the cache memory resource may be configured to perform a read-modify-write operation that may increment or decrement the present control variable value to generate the updated control variable value, and may overwrite the present control variable value stored in the cache memory resource with the updated control variable value. Other examples of such relatively simple read-modify-write operations may read a first data value from the cache memory resource, perform a logical XOR, AND, or OR of the first data value with a second data value supplied from a host/disk controller, and store the results thereof in the memory location from which the first data value was read.
It may be possible to improve the utility, versatility, and effectiveness of the cache memory resource by providing in the cache memory resource means for carrying out read-modify-write memory operations that involve relatively more complex arithmetic and/or logical operations than those that may be performed by the cache memory resource in the Assignee's conventional storage system. It would be desirable to employ a novel memory operation protocol that may be used to facilitate the execution of such relatively complex read-modify-write memory operations, as well as other memory operations, in the cache memory resource.
SUMMARY OF THE INVENTION
In accordance with the present invention, a memory system and method of using same are provided, wherein a novel memory operation protocol may be used to facilitate the execution of memory operations in the memory system. The memory operations whose execution may be facilitated by the present invention may include atomic read-modify-write operations that may involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the Assignee's conventional data storage system.
In one embodiment of the present invention, the memory system may be a shared cache memory resource in a network data storage system, and may include a first logic section and a second logic section. The first logic section may cause a respective assertion of a first signal; the second logic section that may cause, in response to the respective assertion of the first signal, a respective assertion of a second signal. The first logic section may be configured to provide to the second logic section, contemporaneously with the respective assertion of the first signal, information related to a requested memory operation (e.g., a memory operation requested by a host/disk controller in the network data storage system) that is to be performed by the memory system. The information may specify the requested memory operation and one or more memory locations in the memory system upon which the requested memory operation is to operate.
In this embodiment, if the requested memory operation comprises a first type of memory operation, the first logic section may transmit, in response to the respective assertion of the second signal, one or more data words to the second logic section to be used in the requested operation. The first l
MacLellan Christopher S.
Walton John K.
Chace Christian P.
EMC Corporation
Gunther John M.
Gupta Krishnendu
Yoo Do Hyun
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