Static information storage and retrieval – Read/write circuit – Simultaneous operations
Patent
1997-03-20
1998-10-20
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Simultaneous operations
365221, 365236, 36523002, 365239, G11C 700
Patent
active
058256920
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention is directed to a memory means and a method for simultaneously reading and writing data. Inventive memory means are needed, for example, in the compression and decompression of image information. An image that, for example, contains a graphic, text or the like, is composed of a plurality of picture elements, what are referred to as pixels, that are arranged matrix-like. Each row of this matrix contains a plurality of picture elements that represent either the value "white" or "black". These pixels can then be made visible with a picture screen, a printer or some other image reproduction means. The image information is compressed for transporting or storing an image. The compressed image information can be decompressed and made visible again.
Such compression and decompression methods are known from facsimile technology and are described, for example, in CCITT, The International Telegraph Consultative Committee", Blue Book, Vol. VII-Facsimile VII.3, Recommendations T.0-T.63. Other compression and decompression rules such as, for example, of HP (Hewlett Packard) are employed in addition to these compression and decompression rules defined by the CCITT. Algorithms are applied in these standard rules that not only link the information within a line with one another (for example, Huffman encoding) but that also implement a linking of the image information of two successive lines. A processing unit that implements the linking operation is required in order to undertake such a linking. This processing unit must also have a memory means allocated to it from which a pixel of a reference line required at the moment must always be capable of being read and into which a generated pixel of a current line must be capable of being written.
European reference EP 0 341 272 B1 discloses a decoding means that generates pixels from image information encoded according to CCITT. To that end, a processing means collaborates with a memory means. The memory means contains two separate memories, one of which contains all pixels of the reference line. The pixels generated during the decoding are sequentially written into the other memory in succession. When the current line has been completely decoded, then all pixels of this line are in the memory for the current line. The former reference line is no longer required and the current line should serve as reference line in the decoding of the following line. The memory entries of the memory for the current line are therefore transferred into the memory for the reference line. Subsequently, the decoding of the next line is begun upon employment of the new reference line.
In the Prior Art, an increase in the speed of the processing unit in the decompression of image data is achieved by constructing the memory means with two separate memories that can be simultaneously read and written. However, there is a great need for fast memories due to this increase in speed. This high memory requirement uses a comparatively large semiconductor area. This, however, is generally not available since the image processing means is usually realized by an integrated circuit in the form of an ASIC (Application Specific Integrated Circuit). High demands made of the processing speed can be met with these components. Due to the limited area available on an ASIC, the area required for the memory means must be reduced to a minimum. Due to their area requirement, in particular, memory structures of a video RAM can definitely not be implemented in an ASIC given current technology. A transfer of the memories out of the ASIC can be undertaken but is generally not desirable.
U.S. Pat. No. 4,987,559 discloses a memory means (video RAM) with shift registers for the serial reception of data and for the serial output of data. The data are respectively transmitted into a matrix memory or, respectively, output therefrom in parallel. A critical basis for the functionability of the known memory means is the length of the shift register adapted to the plurality of columns of the mat
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Baumgartner Robert
Groger Hans-Detlef
Nelms David C.
Siemens Nixdorf Informationssysteme Aktiengesellschaft
Tran Andrew Q.
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